The present invention relates to a multi-layer ceramic capacitor including side margins provided in a subsequent step, and to a method of producing the multi-layer ceramic capacitor.
Along with miniaturization and achievement of high performance of electronic devices, there have recently been increasingly strong demands for miniaturization, increase in capacitance, and the like with respect to multi-layer ceramic capacitors used in the electronic devices. In order to meet those demands, it is effective to enlarge an intersectional area of internal electrodes of the multi-layer ceramic capacitor as much as possible.
For example, Japanese Patent Application Laid-open Nos. 2012-191159 and 2014-204116 each describe a technique in which side margins for ensuring insulation properties of the periphery of the internal electrodes are provided to a multi-layer chip in a subsequent step, the internal electrodes being exposed to the side surfaces of the multi-layer chip. This technique makes it possible to form thin side margins and relatively increase the intersectional area of the internal electrodes.